Please use this identifier to cite or link to this item: http://192.168.98.239:8080/jspui/handle/1994/1340
Title: Scale length determination, complete 2-D potential modelling and enhancement of some performance parameters of junction less transistors
Researcher: Sarma, Kaushik Chandra Deva
Guides: Sharma, Santanu
Keywords: Electronics & Communication Engineering;Applied physics;Transistors
Award Date: Jan-2017
Department: Department of Electronics & Communication Engineering
Publisher: Tezpur University
Upload Date: 5-Mar-2019
Series/Report no.: T568;
Abstract: Available
Pagination: xxviii, 326p.
URI: http://192.168.98.239:8080/jspui/handle/1994/1340
Appears in Collections:Theses

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01_title.pdfTitle page31.75 kBAdobe PDFThumbnail
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02_abstract.pdfAbstract89.19 kBAdobe PDFThumbnail
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03_declaration.pdfDeclaration of the researcher30.35 kBAdobe PDFThumbnail
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04_certificate.pdfCertificate of the research supervisor43.39 kBAdobe PDFThumbnail
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05_acknowledgement.pdfAcknowledgements22.39 kBAdobe PDFThumbnail
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06_list of publications.pdfList of publications34.12 kBAdobe PDFThumbnail
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07_contents.pdfTable of contents33.79 kBAdobe PDFThumbnail
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08_list of figures.pdfList of figures106.41 kBAdobe PDFThumbnail
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09_list of tables.pdfList of tables16.91 kBAdobe PDFThumbnail
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10_chapter1.pdfChapter 1: Introduction163.25 kBAdobe PDFThumbnail
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11_chapter2.pdfChapter 2: Literature review322.3 kBAdobe PDFThumbnail
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12_chapter3.pdfChapter 3: Scale length determination of some non-conventional structures of JLT603.61 kBAdobe PDFThumbnail
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13_chapter4.pdfChapter 4: Depletion width, threshold voltage and potential modelling of JLT797.17 kBAdobe PDFThumbnail
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14_chapter5.pdfChapter 5: Drain current modelling of double gate JLT479.8 kBAdobe PDFThumbnail
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15_chapter6.pdfChapter 6: Enhancement of performance parameters of JLT1.78 MBAdobe PDFThumbnail
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16_chapter7.pdfChapter 7: Conclusion93.57 kBAdobe PDFThumbnail
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